The present invention relates to a digital-to-analog converter arrangement. More particularly, the invention relates to a digital-to-analog converter arrangement for processing at least two different formats of digital data, which is usable for example in a multi-standard DSL (Digital Subscriber Line) analog front end.
In a multi-standard DSL analog front end, different data formats have to be processed, for example ADSL (Asymmetric Digital Subscriber Line) and VDSL (Very High Bit Rate Digital Subscriber Line), with the requirements for these two examplatory data formats given roughly in the table below:
As can be seen from the above table, the signal frequency range and the performance requirements for the two standards are quite different. Thus, for processing these signals, there is generally no common circuit solution that is optimal in terms of both power consumption and chip area consumption and which is able to process both types of signals. This is especially true for data converters used in the analog front end.
In a transmit path of such an analog front end, a digital-to-analog converter (DAC) is used to convert a digital signal coming from a digital signal processor (DSP) into an analog signal, which is subsequently filtered and amplified before it is applied to a transmission line.
In the following, digital-to-analog converter arrangement according to the state of the art for the above-described two different DSL standards are explained.
FIG. 2 shows an example of a segmented current steering DAC, as described for example by Chi-Hung Lin and Klaas Bult, xe2x80x9cA 10-b, 500-MSample/s CMOS DAC in 0.6 mm2xe2x80x9d, IEEE J. Solid State Circuits, Vol. 33, pp. 1948-1958, the content of which is incorporated by reference herein. In the DAC shown in FIG. 2, a digital input signal a having, for example, a bit-width 12 bits 0 . . . 11 is fed to segmenting means 1. Segmenting means 1 forward the lower bits, for example bits 0 to 3, as a signal d to a digital-to-analog converter 2 consisting of binary current cells 3. In the example, digital-to-analog converter 2 comprises four binary current cells corresponding to the four bits of signal d. Each binary current cell 3 is activated or deactivated according to the state or value of one of the bits of signal d. The least significant bit (LSB), i.e. bit no. 0, of signal d, corresponding to the LSB of signal a, activates a binary current cell which is adapted to output a current of a relative magnitude of 1, the bit no. 1 of signal d causes a current of a relative magnitude of 2, bit no. 2 of signal d causes a current of a relative magnitude of 4 and bit no. 3 of signal d finally activates a binary current cell 3 which is adapted to generate a current of a relative magnitude of 8. The currents output by digital-to-analog converter 2 are added to form an output signal e.
The upper bits of the digital input signal a are fed to a thermometer encoder 6 as a signal c. In the example, signal c consists of the eight bits nos. 4-11 of the digital input signal a.
In the thermometer encoder 6, this 8 bit signal c is converted to a thermometer encoded signal 1. Since with eight bits values from 0 to 255 are representable, in this case the thermometer encoded signal consists of 255 bits, the number of bits set to 1 representing the value of the 8 bit signal c. The thermometer encoded signal 1 is then fed to an array 8 of unary digital-to-analog converting elements 9 which are realized as unary current cells, that is, each digital-to-analog converting element 9 outputs the same current if activated. The array 8 comprises at least 255 of these unary digital-to-analog converting elements 9, and each bit of the thermometer encoded signal 1 is applied to exactly one unary digital-to-analog converting element 9. In the example, the output current of an activated digital-to-analog converting element 9 has a relative magnitude of 16. Thus, a number of digital-to-analog converting elements 9 equal to the value of the 8 bit digital signal c is activated, and their output currents are added to form an output signal f. Output signals e and f are added by adding means 10 to form an output signal g, the magnitude of which corresponds to the value of the digital input signal a.
The use of the array 8 has the advantage that the conversion of the digital input signal a is highly linear, while the conversion of the lower bits by the binary weighted current cells 3 serves to reduce the chip area necessary. For converting all 12 bits of the digital input signal a through the array 8, 4095 unary digital-to-analog converting elements would be necessary, in contrast to the 255 elements in the example.
Such a DAC as shown in FIG. 2 is generally used for VDSL with moderate oversampling. Additionally, a low order (e.g. first order) digital noise shaping for reducing the noise may be provided, as described in H. Weinberger et al., xe2x80x9cA 1.8V 450 mW VDSL 4-Band Analog Front End IC in 0.18 xcexcm CMOSxe2x80x9d, IEEE ISSCC 2002, the content of which is also incorporated by reference.
In contrast, FIG. 3 shows a digital-to-analog converter appropriate for ADSL. This transmission format generally requires higher linearity and resolution.
In FIG. 3, a digital input signal b is fed to noise reducing means 4, for example a digital noise shaper. As in an ADSL signal much more oversampling compared to a VDSL signal is available, the digital noise shaping can be used to increase the in-band resolution. The thus generated noise-shaped digital input signal k is fed to a thermometer encoder 6, as in FIG. 2. This thermometer encoder again generates a thermometer encoded signal 1 from the noise-shaped digital input signal k. For example, if the digital input signal b consists of seven bits 0 . . . 6, the thermometer encoded signal 1 correspondingly comprises 27xe2x88x921=127 bits. This thermometer encoded signal may be directly applied to an array 8 of unary digital-to-analog converting elements 9. However, to improve the linearity of the DAC, dynamic element matching means 7 may be additionally provided. Through these dynamic element matching means 7 a dynamic element matching algorithm is applied, so that the digital-to-analog converting elements 9 of the array 8 are not addressed in a fixed order by the individual bits of the thermometer encoded signal 1, but in an arbitrary order. Such an algorithm is described in U.S. Pat. No. 6,462,691 B2, the content of which is again incorporated by reference.
A straightforward approach to implement the DAC in a multi-standard DSL analog front end is to use optimized CACs as shown in FIGS. 2 and 3 for both transmission formats and select the appropriate one by digital control. Although this solution will be optimal with respect to power consumption, it will suffer from a significant silicon area overhead, since two separate arrays 8 of digital-to-analog converting elements are required. Furthermore, also analog multiplexers are needed for multiplexing the output of the two implemented DACs, which easily degrade the quality of the output signal.
It is thus an object of the present invention to provide a digital-to-analog converter arrangement capable of processing data formats with different requirements which minimizes the needed chip area while keeping the power consumption low.
To achieve this object, according to the invention a digital-to-analog converter arrangement is provided, comprising a first input terminal for receiving a first digital input signal, a second input terminal for receiving a second digital input signal, switching means being coupled to the first and second input terminals and being adapted to select between the first and second digital input signals so as to output an intermediate digital signal corresponding to the selected one of the first and second digital input signals, and an array of unary digital-to-analog converting elements coupled to the switching means for receiving the intermediate digital signal therefrom, each unary digital-to-analog converting element being adapted so that, as an analog output signal, a sum signal of output signals of the unary digital-to-analog converting elements is output.
In such a digital-to-analog converter arrangement, a single array of unary digital-to-analog converting elements may be used for the conversion of both the first digital input signal and the second digital input signal, thus saving chip area.
In a preferred embodiment, thermometer encoding means are coupled to the switching means and to the array of unary digital-to-analog converting elements, said thermometer encoding means being adapted to convert the intermediate digital signal to a thermometer encoded intermediate signal, whereby each bit of the thermometer encoded intermediate signal is applied to a different unary digital-to-analog converting element. The unary digital-to-analog converting elements may be current sources activated according to the state or value of the respective bit of the thermometer encoded intermediate signal applied to them.
To improve the linearity of the digital-to-analog converter arrangement, dynamic element matching means may be provided.
Advantageously, the array of unary digital-to-analog converting elements comprises at least 2nxe2x88x921 unary digital-to-analog converting elements, n being the larger one of the bitwidths of the first and second digital input signals.
Quantization noise reducing means may be used especially in cases where at least one of the digital input signals has a high oversampling.
To process, for example, VDSL signals, the digital-to-analog converter arrangement may further comprise segmenting means having a third input terminal for receiving a third digital input signal, the segmenting means being adapted such that a predetermined number of upper bits of the third digital input signal is output to one of the first or second input terminals, thus forming the first or second digital input signal, while the remaining lower bits of the third digital input signal are output to further digital-to-analog converting means for converting these lower bits of the third digital input signal into a further analog output signal. These further digital-to-analog converting means may comprise binary current cells. The further analog output signal and the analog output signal of the array of unary digital-to-analog converting elements may then be added to form an added output signal.
The digital-to-analog converter arrangement may be realized as an unipolar current steering digital-to-analog converter arrangement or as a fully differential current steering digital-to-analog converter arrangement, e.g. for use in a multi-standard DSL modem.
Preferably, the first digital input signal is a VDSL signal, while the second digital input signal is an ADSL signal. As a matter of course, however, the present invention is not limited to these particular data formats, but may be applied in general to any possible digital data formats.